[Autogenerated] This brings us to the End of this module we
started with Traps which are exceptions.
And interrupts.
And focused on interrupt in this module Look at how
hard to interrupts in concept.
Are waking up, a processor, and saying, hey,
we have to run this inter up up service routine because something
interesting has happened from a hardware device perspective.
Usually some eye operation has completed.
We've seen how I R Q L S determine the power of a particular processor when
running certain code every processor has its own I R Q L.
And always tries to run the highest I Q L.
Code possible in a different perspective,
the R Q L is also a property of an interrupt,
signifying the priority of that interrupt.
We've seen the common levels of R Q L S,
that are defined where RQ 2 or higher changes the rules of the game.
So to speak in that in the that sense there, is no more waiting.
The scheduler can't really wake up on that processor.
So you can't access page out memory, and can't wait.
There's no context which you have theoretically.
An an infinite quantum then We looked at PCs as a mechanism.
To run, code in a lower R Q L which is not as high as I R Q L for interrupt,
but also not as low as as allowing user mode code to run.
So D PCs always run into R Q L two, no more no less.
We don't know which thread.
Is running, that That's usually the thread,
that was interrupted, to run the intra app service routine,
that was running before but could be really any thread because it could also
be an idea ideal thread coming from a different processor,
in the Next, module We'll look at exceptions which is Another aspect of traps.