[Autogenerated] the original anti kernel supported 32 bit physical
addresses and that's because intel supported that However,
in 1996 intel came out with the painting pro processor that was still 32-bit
but supported accessing more than four gigabytes of frame.
And so Microsoft had to enhance the windows kernel which is known as
the physical address extension or pE kernel So the addressing scheme
had to change in the following way and I'll explain why that makes
sense once we get through the slide.
So the basic idea was very similar to the previous case.
We still have an input of a 32 bit address where the lower 12 bits are still
just going to be copied as is the final physical address but now RAM could be
bigger RAM could be more than four gigabytes.
And so a 32 bit value could have been translated to a physical
address which was more than 32 bits in size and solo,
let's see what that would look like in terms of translation.
The previous scheme had to change and it's not immediately
obvious why but let's see how it was changed and then we'll
explain why that was necessary.
So now we have this new split here between nine beats
nine beats and two bits are left.
The data structures is always in physical memory is now a different one called
the page directory pointer table or P D P T if you will,
that has these four entries Because these entries can be selected by
these two most significant bits from the virtual address.
So we have again cr three and K process pointing to that location
of these data structure in physical memory.
Of course this of course again is never paged out.
So now when we have these two bits,
they can select one of potentially four page directories.
Each one of these entries is known as Space Directory,
pointer table entry and the entries have been extended
to 64-bit you might be wondering why.
And the reason is that 32 bits weren't enough to hold on to a larger offset.
Now that had to point to larger addresses in physical memo And also hold
on to more flags that were there as part of the entry.
So Intel had to extend those entries to 64-bit eight bytes in size and this
would allow accessing larger addresses in physical memory.
So these two beats are selecting one of those and this one would point of
course to one of the possibly four no more than that page directories which
as you recall from the previous slide we had just one page Director but now
we have up to four page directories.
Each page directory now has 512 entries and this is perhaps
the confusing part or the interesting part.
Why did interchange the scheme to use nine bits?
Why not just leave the 10 bits scheme from the previous translation when we had
the original anti kernel And so the problem is that every page director in
every page table cannot span more than a single page in size which means they
have to be four kilobytes in size at most.
In the previous case we had 1024 entries times four bytes,
that's exactly four K which is one page.
But now since every entry has had to be extended to 64 bits to
eight bytes then in order to complete the page you can only
have 512 entries which is nine bits.
It requires nine bits to map in fully.
And so that's why we had only 512 entries and this is why
these other two bits were necessary to insert another level
of indirection into the picture.
So we had the same scheme from that point on the first nine beats the
higher nanny beats select a particular page directory.
Sorry,
particular page table and then that page table is going to be
selected selecting a particular page table entry by using the last
remaining nine bits from the address.
That makes sense.
And that P.
T.
Will point finally to the beginning of the page in physical
memory and the final 12 bits will complete the offset and
getting to the real bite that was targeted.
And of course as usual, bit zero still serves the same purpose.
If bit zero is zero it means the actual information there
is invalid and the CPI will not move forward but instead
raise a page fault exception.
So this is how X six X 86 pE virtual translation works.
And the idea here is that the offset within the P T or the
number of bytes bits used here is not just 20.
In fact it was 24.
So if you add 24 with 12 coming from the offset,
you have 36 bits which allows the system to map 64 gigabytes of RAM and
that was what was supported at the time at least.
That's what Microsoft supported for.
32 bit systems that were using that Colonel.
And using those newer processors at the time you could connect up to 64
gigabytes of RAM to a 32 bit system and of course every process wouldn't be
able to use that much memory at any single point in time but it could use that
using certain APIs that were provided by windows known as the p APIs and I
will describe them in a later module