And now we are ready to test all of this logic on its own, so let's create a new BWF.
And that's all the notes.
All right, so that I said this as a top level.
All right, so let us save this file now and we're going to call it FSM.
Now we need to set it as a top level and we need to compile.
Let's see if we are having any issues in the syntax.
And we have some issues, let us check them out.
We forgot the end if here.
At the same for anything else, and we have another issue, let's check it out.
We wrote an instant off and.
Let's check if we have anything else.
We have an end to process here.
I'm in the process for this process and we have already in the process, so that was an extra one that
we have just deleted.
And lastly, all right, we cannot go the state with the same as the signal name.
So this will give us an error.
So I'm going to change this s.E.C.
To accumulate.
And well, also, when you are jumping to accumulate state.
We need to rename it.
And also, the accumulate state itself needs to be renamed.
All right, let's do this again, and we are through we have started compiling and we're done compiling,
so we are ready to start the BWF simulation.
Let's create a new VW file.
And let us list everything and.
OK.
Those are our signals, let us put the.
Outputs and inputs separately, and I want to save this file.
I'm going to call it for some.
The same as my entity name, save it simulation settings, restore defaults and delete this save and
we are ready now to start simulation.
So I need a clock.
The way we simulate the clock is by either putting one zero one zero one zero like that or using the
count command here.
So we need count value and let us count every one hundred nine seconds, OK.
Next, when they have a start.
I want to see what's going to happen.
If I simulate if I have a thought right here, we should be jumping into the state machine, right?
So let us simulate this and see what's going to happen.
Now, what's the first thing we want to do, we want a reset in order to bring the whole the state machine
into the interstate, so we've got to reset.
After resetting, we need to head on start.
So this is my start.
And make sure it is at the falling at.
Let us simulate.
And that's a great we reset it, we are at the interstate, then we head start and we see that the value
of or and or be the value of registering and register, we are being written on their own.
And then we see that right.
See right here is being written.
That's a great but somehow or another we are extending more than necessary.
I mean, take a look at the falling engineer.
We have recognized that there was a start.
So we jump to fetch numbers.
St..
Immediately here at the Golden Gate.
And because we recognize the start, but as you can see, this should last only until here, this is
the process state starting this cycle and well, this or A or B is extending way too long, way too
much.
I mean, if the data changes at this cycle, this will cause us problems.
So maybe we need to shut down this in order to do that.
Let's go to process and specify what should the output.
Be at least four and or be so my dog and or be I would like them to be zero at this point because I
don't want to write in your values.
So let us compile again.
Now, in addition to that, how about we create creative output variable that will show us in which
state we are right now?
It will be very useful to see in simulation in which to state we are at every simulation instance.
So let us create this valuable right here.
I'm going to say state.
Out is actually an output of STD logic vector.
What should be the length of this vector?
Well, how many states do we have?
One, two, three, four, five.
So in order to cover all five, we need three bits.
So it's going to be two down to zero in order to encode every state.
So let's say we are at the first stage right here.
What I want to do is.
I'm going to encode this so that state.
Out this is only a comment equals two zero zero zero, so.
We are going to say St..
Out equals.
Double quotation, zero zero zero.
And like that, now, if you notice, there is a single rotation and double quotation, if you are trying
to represent only one bit, you need only a single quotation.
When you are trying to represent a bus, you need a double quotation.
So we are saying that all the bits of zero when we are in the in its state.
Now let us copy this and do it for all the other states.
So but the difference here in fetch, it's zero zero one.
And accumulate it is 010.
Meaning to actually in the process.
It is.
011 meaning Guitry.
And finally here and right result.
We have one zero zero meaning for.
OK, now let us simulate again.