Welcome back.
So in this lecture, what we're going to do is we're going to design the multiplex here, but using
gate, so we're going to see how we can use Gates in order to design that logic port.
So let us get started.
This will help us understand the internal structure of Multiplex.
We have already seen that in the lecture.
But now let us let us put it in execution.
So we're going to learn something new.
We're going to go to new.
And this time we're going to add a block diagram schematic.
So we're going to go graphical right now.
Now, using this sheet, we can create components and interconnect them together using graphical methods.
So let us go to simple tools.
And if you go here and go to primitives, we're going to see multiple folders.
If you go to logic, you will see multiple gates you have and gates like this is the 12 input and gate
we have.
We have NAND gates and we have no Gates X or any gate you want.
You can find it here.
So what we want is an end gate with two inputs.
So if you don't remember how it looked like a multiplexing using Gates, I'm going to show you now.
This is a multiplex they're using Gates.
Remember, we started with the truth table and we were going to execute this.
So we have one, two, three, four, four and Gates and the other three input and Gates and one for
input or gate in addition to multiple, not gates.
So let us start designing this.
First of all, we need a three input and gate.
We need one to.
Three and four.
Next, we're going to look for a full input or gate, let's search for input or gate.
And this is a Forgan pathology like that, and we need for not Gates, so let us get not Gates.
We need one here to hear.
And one here.
All right.
Let us organize things a bit and we can zoom in, of course.
If you right click, click on Zoom In or control the space, we can zoom in now, we can arrange this
stuff a little bit.
Great.
Now let us do the interconnections.
There is two interconnections here.
This one is a bus interconnection, which we will see how we can use it later.
But this is a bit of a single line connection.
This is a multiple lines connection, like a bus.
Now, let us start connecting this.
Got this one.
This one, just like at the tip of the or gate of the gate and the tip of the output of the gate, and
you should get a connection.
All right, now, let us just pull this a little bit forward.
All right, and we have connected this now let us continue.
We need to connect the last.
In Bouttier.
The last two inputs here.
This is literally according to the schematic with just so.
And we need to connect this as well.
Great.
Now we need to create three inputs and one output, how do we as inputs you go to simple tools and simply
you just go to PIN.
You have inputs and you have outputs, we need a couple of inputs.
We can just put it like that and then rotate it, so let's just put one right now, right, click and
rotate by 270 degrees.
That's correct.
That I zoom out a bit.
Right, like zoom out.
OK, let's pull up a little bit like that so that we have some space and copy paste, control C and
control V, so let us just control C, this control V.
This is the second input again.
Control V.
Again, control, we hear.
And by that, we have our know we need to rename this, so this is my zero.
We can zoom in a little bit.
So that we can see better.
So this is I zero, this is not a 10, by the way.
This is zero.
You know what, you can we can call it.
Input.
Zero.
I'm going to call this input one and let's call this select or Yesil, right?
To zoom out a bit.
We need to create one output as well.
So go back here and choose an output in the bin folder.
Great, now that is interconnected again, using the single line.
OK, now we're going to call this mux, underscore Outteridge, or you can call it whatever you want.
All right.
Now, let us start interconnecting.
According to the schematic, I zero is connected to all of the.
So I, I will be connected to the first input's of all the and gates, I want to be connected to the
second input's of the gates and of course we have to like it's connected to the last.
So let us get started.
So we're going to connect this to the first input.
We can take from this line and distribute.
I can take from this line and distribute.
Same thing here.
All right, I believe we have a mistake here, this needs to be connected to the first input, according
to the schematic.
Then we have the second and the third, then we have the third.
Yes, that's much better.
So that is interconnected.
Yeah.
This is much better and no, let us continue.
So I Ziga will be connected to all of the first input's of all the arrogates input, one would be connected
to the second input of all the and Gates and the select will be connected to the third input of all
the kids.
So that I start with input zero.
I'm going to take input zero here and connect it to the first input which is going to the node, Kate.
Now, the second input here is going to go all the way here and it's going to connect to the first input.
Now, let us distribute from here to this one and let us distribute it from here to this one.
So it's the same point.
All of these are connected with zero, as you can see next second input.
Let us take it.
And interconnected.
Let's do that for the second and let us do that.
For the second year.
And let us do that for the second year, OK?
Now, the last input will be connected to the third input of all the and gates.
So this is the select line that's going to go here.
It's going to be out of this not great.
So this is not great.
And finally here, so this is what the multiplexed looks like from inside.
It looks really good.
That is really amazing.
No, how about we start compiling this in order to do that, we need to save this.
So file save as had I.
Actually, I'm going to call this mux.
Okay, so it's a two to one right, to inputs like the gates here, meaning using Gates.
Let's save it great, next, let's set it to set has double level and of course, compile.
And by that, we're done with compiling and now let's create the way for sort of new and we need a VW.
OK, Internode does not find the same thing and put one to silicon.
We have everything click OK.
Of course, we need to go to simulation simulation settings and restore default, cancel simulation
simulation settings.
And we saw default that has to lead this like save and that while we're going to get an error as well.
But first, let's save the file.
It's called two to one.
MOCs.
Gates, so it's the same name now let us go back to simulation and restore default.
I'm going to this line.
Save and now before we simulate it, to prepare the input output, so my my input is.
Let's say one here.
Zero here, and then I want my input to be one here and zero here.
And.
That's it, this should be enough.
So here, I want my.
Imperturbably one.
So he might be desirable.
And here I want my input to be one.
So what do we expect when selected zero input, zero should pass.
So we should see one and one select is one.
We should see input, one passing, which is also one.
So we should see a one way for between zero and two hundred forty nanoseconds.
So let us compile.
Started this bunch.
Let it go.
We seem to be having an error.
Let us try the simulation settings again, that as we start default, let us try this one more time.
See what went wrong, maybe we did something in this file with something unnecessary think.
OK, it's good that we've fallen in this issue.
Here's the thing, it's not allowed to name files, starting with numbers.
It's very good that we have encountered this error.
So what I want to do is I want to save this project as Max Gates and then we put the two one at the
end of the file name like Save.
And let us remove this file right now from the project by the name of the waveform as well.
And I want to recompile I will said this to top entity.
I want to recompile.
So file names, starting with numbers or symbols, are not allowed in quarters.
They will go some issues.
This what this is what the VW was complaining about, that your file name is really problematic to me.
I can not really compile properly.
So let us fix this issue.
Great.
Now I want to create a new file.
Let's create this from the beginning so that file is already done so.
University program BWF and third node's same thing include everything plays a key role in setting sail
and restore defaults to lead this and save.
And then I want to.
I'll save this, it's going to be called mux.
Gates, to one, save it now we're going to have some issues that's totally okay, simulation settings,
restore defaults and lead this line.
Click save, and now we said we want you to be zero, let's say one.
And here we want one zero.
I think the last time we did it the other way around.
It doesn't matter.
The select line should be one here and the other one here so that this one will pass you here, meaning
input zero will pass now with a simulation.
And.
We got another comment issue, so let us go back simulation, let us restore default one more time and
just delete this.
Like save, let's bring in.
Of.
And here we go, we got to this, so it's good that I am falling in these areas because if you follow
them, at least you know how to solve them.
That's a great the simulation is as expected.
We're getting a one way form on both of these.
Means that one is passing from here to here.
Everything in between is blessing and from here to here receiving input.
Zero is betting.
That's a great.